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CXB1455R
VGA/SVGA/XGA 24-bit Transmitter
Description The CXB1455R is the IC which transmits the 24-bit VGA/SVGA/XGA definition moving picture based on the GVIF (Gigabit Video Interface) technology. Features * 1 chip transmitter for serial transmission of 24-bit color VGA/SVGA/XGA picture * On-chip PLL synthesizer * On-chip differential cable driver * TTL/CMOS compatible interface * Supports 1 pixel/shift clock mode with 1 chip and 2 pixel/shift clock mode with 2 chips * Single 3.3V power supply * Low power consumption * 48-pin plastic QFP package (7mm x 7mm) Application Gigabit video interface 48 pin LQFP (Plastic)
Structure Bi-CMOS IC Absolute Maximum Ratings * Power supply VCC * Operating temperature Topr * Storage temperature Tstg * Allowable power dissipation PD
4.2 0 to +85 -65 to +150 333
V C C mW
Block Diagram and Pin Configuration
SDATAN GNDA GNDT REXT VCCA VDD
Recommended Operating Condition Supply voltage 3.3 0.3
SDATAP CKPOL LPFB LPFA GND CE
V
36 35 34 33 32 31 30 29 28 27 26 25
GND 37 REFREQ 38 CNTL 39 DE 40 SFTCLK 41 HSYNC 42 VSYNC 43 B7 44 B6 45 B5 46 B4 47 VDD 48 Encoder P/S Converter PLL Cable Driver
24 23 22 21 20 19 18 17 16 15 14 13
VDD R0 R1 R2 R3 R4 R5 R6 R7 G0 G1 GND
1 GND
2 B3
3 B2
4 B1
5 B0
6 G7
7 G6
8 G5
9 10 11 12 G4 G3 G2 VDD
Fig. 1. Block Diagram and Pin Configuration
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
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E98Y03B03
CXB1455R
Pin Description Power Supply/Ground Symbol VDD GND VCCA GNDA GNDT Pin No. 12, 24, 36, 48 1, 13, 25, 37 34 35 32 Description Logic power supply; connected to 3.3V 0.3V Logic ground; connected to 0V Analog power supply; connected to 3.3V 0.3V Analog ground; connected to 0V Transmission ground; connected to 0V
Digital Signal Symbol SFTCLK 41 16, 17, 18, 19, 20, 21, 22, 23 6, 7, 8, 9, 10, 11, 14, 15 44, 45, 46, 47, 2, 3, 4, 5 42 43 39 40 TTL in 1 Hsync data TTL in 1 Vsync data TTL in 1 Panel control data TTL in 1 Data enable
VDD
Pin No.
Type
Description
Equivalent Circuit
Shift clock, for the data TTL in 1 fetch at rising or falling edge
VDD
RED (7 to 0) GRN (7 to 0) BLU (7 to 0) HSYNC VSYNC CNTL DE
TTL in 1
Pixel data. 1 pixel/shift clock input.
TTL-IN
GND
CE
26
TTL in 2 Chip enable
TTL-IN
CKPOL
29
TTL in 2 SFTCLK polarity
GND
VCCA
SDATAP
SDATAP/N
30, 31
Tx
Serial output and Refclk request input
SDATAN
VDD GNDT GNDA GND
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CXB1455R
Symbol
Pin No.
Type
Description
Equivalent Circuit
VDD
REFREQ
38
TTL out
Refclk request detection flag
TTL-OUT
GND
Special Symbol Pin No. Description Equivalent Circuit
VCCA
REXT
33
SDATAP/N output current trimming. Connect to the external resistor.
REXT
VDD GNDA GND
VCCA
LPFA LPFB
LPFA/B
27, 28
External loop filter
VDD GNDA GND
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CXB1455R
Electrical Characteristics Table 1. Absolute Maximum Ratings Item Supply voltage TTL DC input voltage TTL H level output current TTL L level output current Serial output pin voltage Ambient temperature Storage temperature Symbol VCC VI_T IOH_T IOL_T Min. -0.3 -0.5 -20 0 Typ. Max. 4.2 6.5 0 20 VCC + 0.5 120 150 Unit V V mA ' mA V C C Under bias Remarks
Vsdout VCC-1.2 Ta Tstg -55 -65
Table 2. Recommended Operating Conditions Item Symbol Min. 3.0 0 Typ. 3.3 Max. 3.6 85 Unit V C Conditions
Supply voltage (Includes VDD and VccA) VCC Ambient temperature Ta
Table 3. DC Characteristics (Under the recommended operating conditions. See Table 2.) Item TTL High level input voltage TTL Low level input voltage TTL High level input current TTL Low level input current CE, CKPOL High level input voltage CE, CKPOL Low level input voltage CE, CKPOL High level input current CE, CKPOL Low level input current TTL High level output voltage TTL Low level output voltage SDATA High level output current SDATA Low level output current SDATA High level output voltage SDATA Low level output voltage Supply current GRAYSCALE WORSTCASE ICC Symbol VIH_T VIL_T IIH_T IIL_T VIH_C VIL_C IIH_C IIL_C VOH_T VOL_T IOH_SD IOL_SD -0.1 14.5 0 15.7 -1.0 2.4 0.4 +0.5 17 -1.0 VCC - 0.5 0 5.5 0.5 1.0 Min. 2 0 Typ. Max. 5.5 0.8 1.0 Unit V V A A V V A A V V mA mA V VCC - 0.76 44.0 50.0 61.0 71.0 77.0 92.0 V mA mA VIN = VCC VIN = 0 IOH = -8mA IOL = 8mA REXT = 4.7k Common mode voltage @65MHz See Fig. 8 See Fig. 7 VIN = VCC VIN = 0 Conditions
VIH_SD VCC - 0.55 VIL_SD
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CXB1455R
Table 4. AC Characteristics (Under the recommended operating conditions. See Table 2.) Item TTL input rise time TTL input fall time Minimum SFTCLK frequency Maximum SFTCLK frequency SFTCLK duty factor Pixel/Sync/Cntl setup time to SFTCLK Pixel/Sync/Cntl hold time to SFTCLK SDATA rise time SDATA fall time Clock mode assert time Clock mode deassert time Idle mode assert time Idle mode deassert time PLL lock-in time Symbol Tir Tif Fsftclk Dsftclk Tsetup Thold Tor Tof TAclk TDclk TAidle TDidle Tlockin Min. 0.7 0.7 65.0 40 2.5 2.5 200 200 50 10 150 100 0.1 60 Typ. Max. 5.0 5.0 25.0 Unit ns ns MHz MHz % ns ns ps ps ns ns ns ns ms 20 to 80%, CL = 2pF See Fig. 2. Vth = 1.4V 0.8 to 2.0V 2.0 to 0.8V Conditions
VCC/A TTL clock VCC CXB1455R RGB, CE VS, HS, DE, CNTL, CKPOL GND/A/T
51
51
41 30 100 31 Sampling oscilloscope FET probe
Fig. 2. SDATA waveform measurement
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CXB1455R
Timing Chart
1/Fsftclk Dsftclk/Fsftclk VIH_T 2.0V SFTCLK 0.8V VIL_T Tir Setup/hold times are referred from falling edge in CKPOL = GND rising edge in CKPOL = Vcc REDxx GRNxx BLUxx H/Vsync CNTLx Tif Vth
Tsetup Tir 2.0V 0.8V
Thold VIH_T
VIL_T Tif Min. 2 (SFTCLK cycle)
VSYNC Min. 2 Min. 2 HSYNC Min. 2 Min. 2 Min. 2
DE
RGB
CNTL
There must be 2 SFTCLK cycles or more left between the CNTL edge and the HSYNC, VSYNC and DE edges.
Fig. 3. TTL input timing
Tor 80% SDATAP SDATAN 20% 0% Tof 100%
Fig. 4. Serial output timing
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CXB1455R
Reference clock SDATAP SDATAN REFRQ signal from CXB1454R or CXB1456R REFREQ TDclk
NRZ data
TAclk
Fig. 5. Refclk request timing
CE
SDATAP SDATAN TDidle
NRZ data TAidle
Fig. 6. Idle mode timing
SFTCLK
f
RGB <7, 5, 3, 1>
f/2
RGB <6, 4, 2, 0>
f/2
Fig. 7. Worst case test pattern
SFTCLK RGB <7> RGB <6> RGB <5> RGB <4> RGB <3> RGB <2> RGB <1> RGB <0>
f f/16 f/8 f/4 f/2 Fix Low Fix Low Fix Low Fix Low
Fig. 8. 16 grayscale test pattern -7-
CXB1455R
CE Pin Control The CE pin should be controlled as follows. When the power is turned ON or SFTCLK stops, or when the SFTCLK input signal falls into the disorder while the SFTCLK frequency is varied, the CE pin should be set to Low level and the CE pin should be set to High level after the SFTCLK frequency stabilizes. (Figs. 9 and 10)
When the power supply and SFTCLK stabilize
VCC
SFTCLK
200s or more CE
Fig. 9. CE timing when power supply is turned ON
When SFTCLK does not stabilize
When SFTCLK stabilizes
SFTCLK
200s or more CE
When SFTCLK stops or the frequencies of 15MHz or less and 75MHz or more are input.
Fig. 10. CE timing when SFTCLK input signal is not stabilized
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CXB1455R
CKPOL Pin Control The CKPOL pin selects the SFTCLK data sampling trigger edge. (See Table 5) Table 5. SFTCLK polarity CKPOL L H SFTCLK data sampling trigger Falling edge Rising edge
Applications The CXB1455R GVIF transmitter is applied to the digital RGB signal transmission for P/C with LCD monitor Video-on-demand system Monitoring system Graphical controller Projector Digital TV monitor Automobile Navigation System with GVIF receivers, CXB1454R/CXB1456R.
CXB1455R GVIF Transmitter 8 8 8 4
Encoder
RED (7 to 0) GRN (7 to 0) BLU (7 to 0) SYNC/DE/CNTL SHIFTCLOCK
Parallel to Serial Converter
Cable Driver
PLL
STP or Twin axial
Cable Equalizer
Serial to Parallel Converter
Decoder
8 8 8 4
RED (7 to 0) GRN (7 to 0) BLU (7 to 0) SYNC/DE/CNTL SHIFTCLOCK
PLL CXB1454R/CXB1456R GVIF Receiver
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CXB1455R
Application Circuit
(1) Chip resistor (1%) (2) Chip capacitor (3) Formed by the printed circuit pattern (L = 0.5 to 1.0mm/W = 0.5 to 1.0mm) (4) LPF chip capacitor (Temperature compensation type) VCC 330 Connector VCC 0.1 to 0.4n (3) 33 16V 0.1 to 0.4n (3) 0.1 (2) VCC 51 (1) 4.7k (1) 51 (1) 680p (4) 1k (1) VCC 0.01 (4) 1k (1) 330 SW1 High: Transmission data Low: Standby SW2 High: Rising edge trigger Low: Falling edge trigger
Differential cable
0.1 (2)
36 VCC
35 GNDA
34 VCCA
33 REXT
32 GNDT
31 SDATAN
30 SDATAP
29 CKPOL
28 LPFB
27 LPFA
26 CE
25 GND
0.1 (2) VCC 24 R0 23 R1 22 R2 21 R3 20 R4 19 VCC
37 GND 38 REFREQ 39 CNTL 40 DE 41 SFTCLK 42 HSYNC
CXB1455R 43 VSYNC 44 B7 45 B6 46 B5 VCC 47 B4 GND 48 VCC VCC 12 0.1 (2) VCC R5 18 R6 17 R7 16 G0 15 G1 14 GND 13 G7 G6 G5 G4 G3 10 G2 11 B3 B2 B1 4 B0 5
1 0.1 (2)
2
3
6
7
8
9
CNTL SFTCLK HSYNC VSYNC DE
76543210 MSB LSB BLUE DATA
76543210 MSB LSB GREEN DATA
76543210 MSB LSB RED DATA
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
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CXB1455R
A
E
G SDATAN SDATAP CKPOL
GNDA
GNDT
REXT
LPFB
LPFA
VCCA
G 37 37 GND REFREQ CNTL DE SFTCLK HSYNC VSYNC BLU <7> BLU <6>
GND
VCC
CE
VCC R G P C RED <0> RED <1> RED <2> RED <3> RED <4> RED <5> RED <6> RED <7> T T T GRN <0> GRN <1> GND GND BLU <3> BLU <2> BLU <1> BLU <0> GRN <7> GRN <6> GRN <5> GRN <4> GRN <3> GRN <2> VCC
24
BLU <5> BLU <4> 48 48 VCC
13
G
G 1 12
Microstrip Line The microstrip line with the characteristic impedance of 50 should be used to connect the LSI transmission signal pin SDATAP/N to the connector foot printer as GVIF transmits the high-speed digital signal with the maximum speed of 2Gb/s. The optimal line can be made by forming 0.5mm pattern on L1. (See the board structure shown below.) The line lengths should be the same and the through hole should be not used. Normally, L2 should be the mat GND. Termination Elements Locate the 51 termination resistors as close to the LSI as possible. Filter Device and Reference Resistor The capacitor and resistor connected to LPFA/B and REXT are the filter and the reference resistor. Locate them as close to the LSI as possible. Decrease the parasitic capacitance by removing the L2 GND plane under these elements and wiring. - 11 -
,,
, , , , , , , ,
Recommended Printed Board Structure
L1: I1: L2: I2: L3: I3: L4: Cu plate (18m) + solder coat Fiber-glass epoxy core (0.3mm) Cu plate (36m) Fiber-glass epoxy core (0.8mm) Cu plate (36m) Fiber-glass epoxy core (0.3mm) Cu plate (18m) + solder coat
Recommended Printed Circuit Board Pattern Example of power supply and special signal routing
0.5mm
A
: Through hole to the GNDA plane (L2) : Through hole to the GND plane (L2) : Through hole to the VccA plane (L3) : Through hole to the Vcc plane (L3) : Through hole to the REXT resistor (L4) : Through hole to the CKPOL signal (L4) : Through hole to the CE signal (L4) Chip capacitor Chip resistor
G E T
L2 doesn't have the plane in this area.
R E E P
,, ,,, , ,,,
, ,, ,,, ,,
C
Locate the bypass capacitor (0.1F chip capacitor) as close to the pins as possible.
CXB1455R
By-pass Capacitor Locate a 0.1 F chip capacitor as close to the pin as possible as shown in the Recommended Circuit Diagram. Notes on Transmission System Configuration The GVIF uses termination on both the transmitting and receiving ends, built-in equalizers, small amplitude differential signals, etc. in order to more easily resolve problems such as signal reflectance, signal attenuation and EMI which interfere with high-speed data transmission. However, a number of cautions must be observed over the entire transmission system shown in the figure below in order to completely resolve these problems.
Tx termination 50 Tx termination 100 Tx LSI Rx LSI
Microstrip line (50)
Foot print
Connector
Cable (diff. 100)
Connector
Foot print
Microstrip line (50)
The transmission system has the following four requirements. * Impedance matching shall be excellent. (Reflectance shall be low.) A differential impedance that falls within the template shown on the following page is recommended. * Attenuation shall be low and regular. For the CXB1454R (built-in equalizer) Attenuation of 15 dB (conforming to root f attenuation) @ 1 GHz or less is recommended. See the following page. For the CXB1456R (no equalizer) Attenuation of 6 dB @ 1 GHz or less is recommended. * Differential signal POS/NEG skew shall be small. 12% or less during the time for one bit is recommended. 160 ps @ VGA, 100 ps @ SVGA, 60 ps @ XGA * EMI characteristics shall be excellent. The following measures are effective for satisfying these requirements. * Use a low attenuation, low skew differential cable with excellent impedance accuracy. A cable with a two-core coaxial (shielded twisted pair) structure is recommended. * Use low reflectance connectors. * Take care for the connector pin assignment. Select pins so that there is no interference with other signals and so that the positive and negative signal wiring are the same length on the board. * Use a cable with a double shielded structure.
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CXB1455R
Recommended Transmission Path : Differential impedance template
Zo () 150 110 106 94 90 75
< 500ps
< 500ps
Microstrip line
Foot print
Connector
Cable
Connector
Foot print
Microstrip line
Recommended Transmission Path : Attennation Characteristics
Loss
< 15dB 2dB Measured curve
Fitting curve Frequency 1GHz
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CXB1455R
1.95Gbps SDATAP output waveform
100mV/div 100ps/div
SFCLK jitter tolerance: Example of power spectrum which can be used for transmission
ATTEN 10dB RL 0dBm 10dB/
REF LVL 0dBm D
CENTER 65.00MHz RBW 100kHz
VBW 100kHz
SPAN 10.00MHz SWP 50ms
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CXB1455R
Package Outline
Unit: mm
48PIN LQFP (PLASTIC)
9.0 0.2 36 37 7.0 0.1 25 24 S
(8.0)
A 48 1 0.5 + 0.08 0.18 - 0.03 + 0.2 1.5 - 0.1 12 13
B
(0.22)
+ 0.05 0.127 - 0.02 0.13 M
0.1 0.1 0.1
0.5 0.2
S
(0.127) +0.05 0.127 - 0.02
(0.18)
0.18 0.03
0 to 10
0.5 0.2
DETAIL B:SOLDER DETAIL A
DETAIL B:PALLADIUM
NOTE: Dimension "" does not include mold protrusion.
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE LQFP-48P-L01 LQFP048-P-0707 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER/PALLADIUM PLATING 42/COPPER ALLOY 0.2g
NOTE : PALLADIUM PLATING This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame).
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0.127 0.04
+ 0.08 0.18 - 0.03
Sony Corporation

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